As the minimum feature sizes in integrated circuits become smaller, it becomes necessary to increase the packing density of the devices on the integrated circuit (IC) chip. The benefits of smaller devices are largely forfeited if the distance between devices cannot also be decreased.
FIGS. 1-11 illustrate prior art processes and structures and some of the problems that are inherent in those processes and structures.
FIG. 1A illustrates a common method of fabricating a semiconductor device. A dopant is introduced in an N or P substrate 100 through an opening formed in a mask layer 102, which could be an oxide, a nitride, photoresist, or some combination thereof. The dopant could be introduced by ion implantation or by a high-temperature predeposition (i.e. a shallow diffusion where a source of doping from a gaseous or solid source is introduced into the semiconductor). The dopant may then be diffused by heating to form a shallow region 104 as shown in FIG. 1B, or the dopant may diffused at a higher temperature or for a longer time to form a much deeper region 106, as shown in FIG. 1C. Region 104 could be 0.5 to 2 μm deep and region 106 could be 2 μm to 10 μm deep. FIG. 1D is a view of the left side of region 106, showing in detail the lateral spreading of region 106 during the thermal diffusion process. As indicted, the junction dopant spreads laterally as well as vertically during the diffusion. As a general rule, the lateral spreading from the point (0,0) at the edge of the mask opening is equal to about 0.8 times the vertical depth (xj) of the junction. This lateral spreading of dopant limits the horizontal spacing and packing density of devices formed using a conventional thermal diffusion process.
FIGS. 2A and 2B illustrate another problem with diffusion processes, i.e., the depth of the junction can be a function of the width of the mask opening. FIG. 2A shows the results of a diffusion performed after an implant through a mask opening W1, and FIG. 2B shows the results of a diffusion performed after an implant through a mask opening W2, where W1>W2. The final depth of the junction in FIG. 2B is less than the depth of the junction in FIG. 2A by a factor η, which is less than one. This phenomenon occurs because the lateral spreading of the dopant when the mask opening is relatively small reduces the surface concentration and the gradient of the doping concentration in a vertical direction more than when the mask opening is large. Thus the dopant diffuses downward more slowly when the mask opening is small, an effect referred to as “starved diffusion”. Therefore, the mask opening must be relatively large in order get a deep junction, for example, to create a sidewall isolation region for a thick layer. Again, the necessity of a large mask opening limits the packing density of the semiconductor devices.
FIGS. 3A and 3B exemplify some of the impacts of these problems. Ideally, one would like to form a deep diffusion 108 separated from a shallow diffusion 110 by a distance YN+/P+, as shown in FIG. 3A. In reality, because of lateral dopant spreading, a deep diffusion 108 of the form shown in FIG. 3A is not possible. Instead, the result is a much wider diffusion 112 shown in FIG. 3B, which is separated from diffusion 110 by a much smaller distance YN+/P+, despite having the same spacing between the mask features of both N+ and P+ junctions.
A similar problem occurs in the formation of vertical isolation regions and buried layers. FIG. 4A shows an ideal structure that includes a vertical P isolation region 114 extending through an N-epi layer 116 to a P substrate 120. An N buried layer (NBL) 118 is formed at the interface between N-epi layer 116 and P substrate 120. Both P isolation region 114 and N buried layer 118 are sharp, well defined regions with vertical edges, separated by a distance W3. In reality, what happens with a conventional diffusion process is shown in FIG. 4B. N buried layer 118 expands horizontally during the growth of N-epi layer 116 and the subsequent driving-in of P isolation region 114, and P isolation region 114 likewise expands laterally, reducing the separation between N buried layer 118 and P isolation region 114 to a distance W4 that is much less than W3. As a result the breakdown voltage between N buried layer 118 and P isolation region would be reduced and to obtain the breakdown voltage of the structure shown in FIG. 4A, one would have to significantly widen the separation between N buried layer 118 and P isolation region 114.
FIGS. 5A-5F show the steps of a conventional process junction-isolation, i.e., isolation extending downward from the top surface (also known as “down-only” junction isolation.). In FIG. 5A, a thick oxide layer 122 (e.g., 1 to 5 μm thick) has been grown on a P substrate 124. In FIG. 5B, a photoresist layer 126 has been formed on top of oxide layer 122 and oxide layer 122 has been etched through an opening in photoresist layer 126. A thin oxide layer 130 is formed in the opening and a slow-diffusing N-type dopant such as antimony or arsenic is implanted through the opening to form an N buried layer 128, shown in FIG. 5C.
To prepare for the subsequent growth of an overlying epitaxial layer, the surface concentration of dopant in N buried layer 128 must be reduced. This is necessary to reduce the outgasing of dopant into the epitaxial reactor during the growth of the epi layer. To accomplish this, N buried layer 128 is driven in at a high temperature for an extended period of time, e.g., 1100 to 1250° C. for 5 to 20 hours. The length and temperature of this thermal process is made necessary by the fact that for purposes of later processing the dopant used to form N buried layer 128 is one that diffuses slowly, so diffusing it away from the silicon surface prior to epitaxy necessarily takes high temperatures and long times.
FIG. 5D shows the structure after the growth of an N epi layer 132 on P substrate 124. As indicated, N buried layer 128 has diffused upward into N epi layer 132.
As shown in FIG. 5E, an oxide layer 134 is formed on the surface of N epi layer 132 and an opening is etched in oxide layer 134 using a photoresist mask layer 136. A P-type dopant such as boron is implanted through the opening in oxide layer 134 to form P isolation region 136. The entire structure is then subjected to a thermal process, which causes P isolation region 136 to diffuse downward through N epi layer 132 to P substrate 124, at the same time forming a thin oxide layer 138. N buried layer 128 diffuses upward and laterally during this thermal process. Since N buried layer 128 is formed of a slow-diffusing dopant, it diffuses more slowly than the boron in P isolation region 136, and thus N buried layer 128 remains separated from P isolation region 136. Nonetheless, to guarantee this separation, N epi layer 132 must be made thicker than would otherwise be desirable.
FIG. 6 illustrates a way of reducing this problem by forming a P buried layer 140 directly below P isolation region 136. P buried layer 140 diffuses upward during the thermal process and meets the down-diffusing P isolation region 136 sometime near the middle of N epi layer 132, thereby reducing the amount of thermal processing required and the lateral diffusion of N buried layer 128. Nonetheless, such lateral diffusion does occur and wafer space is therefore still wasted.
FIGS. 7A-7F illustrate a process for forming the structure of FIG. 6. FIG. 7A shows the structure after N buried layer 128 has been implanted and thermally diffused to reduce the surface dopant concentration before the growth of an epitaxial layer. During the thermal diffusion process a thick oxide layer 146 is formed. In the event that a high concentration of arsenic is used to form the buried layer, the oxide atop the NBL may grow to a slightly greater thickness than those portions growing over the more lightly doped P-type substrate (an effect known as “concentration enhanced oxidation”). The result may be an oxide layer 142 that has a thickness less than the thickness of oxide 146 despite having the same oxidation time. The phenomena may also occur using antimony as the dopant species, but with a reduced magnitude effect. A photoresist layer 144 is deposited on top of oxide layers 142 and 146 and patterned for the implant of boron ions to form P buried layer 140. The edge of the opening in photoresist layer 144 is spaced a lateral distance W5 from the edge of N buried layer 128 to ensure that N buried layer 128 and P buried layer 140 do not merge during subsequent thermal processing.
As shown in FIG. 7B, oxide layer 142 is etched through the opening in photoresist layer 144, and boron (or another P-type dopant) is implanted through the opening to form P buried layer 140. The structure is again annealed to reduce the surface concentration of P buried layer 140, forming a thin oxide layer 148, as shown in FIG. 7C.
Next, N epi layer 132 is grown on top of P substrate 124 using epitaxial deposition, as shown in FIG. 7D. Normally vapor phase epitaxial (VPE) deposition is preferred over liquid phase epitaxy, especially in the deposition of silicon. VPE, however, requires the substrate to be heated to a high temperature, typically above 1200° C. During the growth of N epi layer 132, N buried layer 128 and P buried layer 140 spread both vertically and laterally, reducing the separation between these two buried layers.
As shown in FIG. 7E, an oxide layer 150 is formed on the surface of N epi layer 132. Oxide layer 150 is patterned using common photolithographic techniques to form an opening through which boron is implanted to form P isolation region 136. As shown in FIG. 7F, the structure is then annealed once again to cause P buried layer 140 to diffuse upward and P isolation region 136 to diffuse downward until these two diffusions merge somewhere within N epi layer 132. N buried layer 128 and P buried layer 140 diffuse laterally during this anneal until the separation between them becomes quite small. Absent the separation W5 shown in FIG. 7A, these two buried layers would in fact merge, and therefore the separation W5 is in effect the “penalty” that must be paid to assure that in the final structure P buried layer 140 is spaced sufficiently from N buried layer 128 to provide the required breakdown voltage.
As is evident, this is a complicated, time-consuming process which can lead to the warping of the wafer, particularly with larger wafers, and to lower yields. Up-diffusion of the NBL during the isolation diffusion also reduces the “flat” concentration portion of N epi layer 132, requiring a thicker epitaxial layer than would be needed if up-diffusion did not occur.
FIG. 8 shows a way of avoiding this problem by etching a trench 152 all the way through the N epi layer 132 and filling trench 152 with a dielectric 154. Trench 152 might have to be very deep to extend entirely through N epi layer 132, since N epi layer could be anywhere from 5 μm to 20 μm thick, for example.
A process for forming the structure of FIG. 8 is shown in FIGS. 9A-9F. After N epi layer 132 has been formed, an oxide or other hard mask layer 156 is deposited on N epi layer 132 and patterned with a photoresist layer 158, as shown in FIG. 9A. An opening 160 is thereby formed in layer 156, as shown in FIG. 9B, and trench 152 is etched through N epi layer 132, as shown in FIG. 9C. This is typically done by a reactive ion etch (RIE).
After trench 152 has been formed, hard mask layer 156 is removed, and a sacrificial oxide layer (not shown) is grown in trench 152 to repair crystalline damage caused by the RIE process. The sacrificial oxide layer is removed and another oxide layer 162 is grown in the walls of trench 152 and top surface of N epi layer 132, as shown in FIG. 9D. Trench 152 is filled with a dielectric material 164 which overlaps the top surface of N epi layer 132, as shown in FIG. 9E, and dielectric material 164 is planarized as shown in FIG. 9F, so that the top surface of dielectric material 164 is level with the top surface of oxide layer 162.
Since trench 152 does not expand or spread significantly during this process, and since it does not form a PN junction to the epitaxial layer, trench 152 can be located closer to N buried layer 128 than, for example, P buried layer 140 at the stage shown in FIG. 7C. Nonetheless, this process has several problems and risks. Because trench 152 can be very deep, it may be difficult to fill. As shown in FIG. 10A, if trench is under filled, a narrow gap may be left extending downward from the top surface of dielectric material 164 conformal to the trench itself, as shown in FIG. 10A, or a narrow void may be left in the trench, as shown in FIG. 10B. If the trench has a narrow mouth, a void may be left in the bottom portion, as shown in FIG. 10C, or if the RIE is somewhat less anisotropic producing a trench with a wide mouth, the dielectric 164 may be removed from the inside of the trench during the etchback leaving only a small portion in the bottom of the trench, as shown in FIG. 10D. In conclusion deep trench isolation and re-fill remains a challenging process for high volume manufacturing
FIGS. 11A-11E illustrate several semiconductor devices formed using prior art diffusion techniques.
FIG. 11A shows an NPN transistor 234 and a PNP transistor 236 that are formed in an N epi layer 202 grown on a P substrate 200. The emitter of NPN transistor is an N+ region 208, the base includes a P+ region (the base contact, or extrinsic base) 210 and a dedicated P-base region (the active transistor or intrinsic base regions) 206, and the collector includes an N+ region 212 (collector contact region), a portion of N epi layer 202 (the collector), and an N buried layer 204A (a so-called sub-collector region). N buried layer 204A isolates transistor 234 from P substrate 200 and lowers the resistance of the collector.
In PNP transistor 236, the emitter is a P+ region 226, the base includes an N+ extrinsic base contact region 224 and a dedicated intrinsic base region 222, and the collector includes a P+ collector contact region 228, a P-well 220, and a P buried layer sub-collector 218. PNP transistor 236 is isolated from P substrate 200 by an N buried layer 204B. N buried layer (NBL) 204B and P buried layer (PBL) 218 are formed at the interface of N epi layer 202 and P substrate 200. N buried layer 204B may be formed with a relatively slow-diffusing dopant such as antimony or arsenic, and P buried layer 218 may be formed with a fast diffusing dopant such as boron. As a result, P buried layer 218 extends above N buried layer 204B, and in some cases may extend both above and below the NBL.
NPN transistor 234 is isolated from PNP transistor 236 by a P isolation region 214, which extends from the surface of N epi layer 202 into P substrate 200. P isolation region 214 also provides a means of setting the potential of P substrate 200 through a P+ contact region 216, and is often biased at the most negative on-chip potential or ground. The potential of the portion of N epi layer 202 in PNP transistor 236 can be set through an N+ contact region 230, where the NBL 204B must be biased at a potential equal to or more positive than P substrate 200 and equal to or more positive than PBL 218. Common practice often involves biasing NBL at the positive supply rail (e.g. Vcc) or shorting PBL 218 and NBL 204B to the same potential (a zero biased junction).
FIG. 11B shows a lateral double-diffused N-channel MOSFET 238 (also known as an LDMOSFET) and an isolated CMOS pair that includes a PMOSFET 240 and an NMOSFET 242. Again, the devices are formed in N epi layer 202. In N-channel LDMOSFET 238, the source is an N+ region 246, the body comprises a P+ contact region 244 and a dedicated P-body diffusion 248 (or P-well 265), and the drain is an N+ region 249 and a portion of N epi layer 202 acting as a lightly doped drain extension. The channel portion of P-body (or P well) 248 underlies a gate 247, setting the threshold voltage of the MOSFET and preventing punch-through breakdown between the source and the drain (by forcing the majority of the depletion spreading of the P-body to N-epi junction into the epitaxial drain side of the device). Unlike conventional MOSFETs whose channel length is determined by the length of the gate region, in this device the difference in junction depth between the body 248 and the source 246 along the surface, i.e. laterally, sets the channel length of the LDMOSFET. In the self-aligned version of the device, P-body 248 is implanted after the gate electrode of the device is formed, after which the junction is diffused for a long time and at high temperatures (e.g. 1100° C. for 14 hours) to achieve a sufficient junction depth and channel length. Since both source and body junction are formed after the gate, the device is self aligned. In the lower cost version of the LDMOSFET, P-well diffusion 265 (used in the CMOS) is used as the body of the device. Since the well is formed prior to the gate it is not self-aligned to the gate, making punchthrough and threshold voltage dependent on mask alignment. A section of N epi layer 202 that separates the channel from N+ region increases the breakdown potential of the device provided it also is adequately spaced from both the P-body region 248 and spaced from isolation diffusion 250.
In PMOSFET 240, the source is a P+ region 256, the body includes an N+ contact region 254 and a portion of N epi layer 202, and the drain is a P+ region 258. The channel portion of N epi layer 202 underlies a gate 260. In NMOSFET 242, the source is an N+ region 264, the body includes a P+ contact region 262 and a P well 265, and the drain is an N+ region 266. The channel portion of P well 265 underlies a gate 268. The CMOS pair and lightly-doped drain NMOSFET 238 are separated from each other by a P isolation region 250. Contact to P substrate 200 is made through P isolation region 250 and a P+ contact region 252. NBL 204 isolates P-well 265 from substrate P substrate 200.
FIG. 11C shows an N-channel quasi-vertical DMOSFET 270, another variant of an N-channel lateral DMOSFET 272, and a fully isolated PMOSFET 274. Quasi-vertical DMOSFET 270 is built as a matrix of cells bordered by gates 276A, 276B and 276C. Each cell of DMOSFET 270 includes an N+ region 280 that functions as a source, and a P+ region 282 and P-body 278 that together function as a body. The source and body are shorted together. The current flows from the source, through a channel under the gates 276A, 276B, 276C, through N epi layer 202, down to N buried layer 204D and then up through an N sinker 284 and an N+ region 286 to the drain terminal (hence the nomenclature quasi-vertical). DMOSFET 270 is isolated from P substrate 200 by N buried layer 204D, which also lowers the resistance of the device.
N-channel Lateral DMOSFET 272 includes an N+ region 298 that functions as a source, and a P+ region 294 and P-body 292 that together function as a body. The current flows from N+ region 298, through a channel under a gate 296, down to an N buried layer 204E and along the surface in N epi layer 202, and then up through an N sinker 300 and an N+ region 302 to the drain terminal. N-channel LDMOSFET 272 is isolated from P substrate 200 by N buried layer 204E and from DMOSFET 270 by a P isolation region 288 and a P buried layer 290.
Isolated PMOSFET 274 includes P+ region 310 that functions as the source and a P+ region 312 that functions as the drain. The body is a portion of N epi layer 202 and is contacted by an N+ contact region 308. The current flows from P+ region 310 to P+ region 312 through a channel that underlies a gate 314. PMOSFET 274 is isolated from P substrate 200 by N buried layer 204F and from NMOSFET 272 by a P isolation region 304 and a P buried layer 306.
FIG. 11D shows another N-channel lateral DMOSFET variant 308, a lateral NMOSFET 310, and a vertical PNP bipolar transistor 312. N-channel LDMOSFET 308 is similar to NMOSFET 238 shown in FIG. 11B (similar components are similarly numbered), except that gate 314 steps up over a field oxide layer and lightly-doped NMOSFET 308 is isolated from P substrate 200 by an N buried layer 204G. N-channel lateral DMOSFET 310 is similar to N-channel LDMOSFET 242 shown in FIG. 11B, except that NMOSFET 310 does not include N buried layer 204.
In vertical PNP transistor 312, a P+ region 314 serves as the emitter, an N-base 316, an N+ region 318, and a portion of N epi layer 202 serve as the base, and a P buried layer 320 and a P sinker 322 serve as the collector. PNP transistor 312 is isolated from P substrate 200 by an N buried layer 204H.
N-channel lateral DMOSFET 308 is isolated from lateral NMOSFET 310 by a P isolation diffusion 324 and a P buried layer 326, and lateral NMOSFET 310 is isolated from vertical PNP bipolar transistor 312 by a P sinker 328 and a P buried layer 330.
FIG. 11E shows devices formed in a P epi layer 342 that is grown on a P substrate 340. A CMOS pair includes a PMOSFET 344 and an NMOSFET 346. PMOSFET 344 and NMOSFET 346 are similar to PMOSFET 240 and NMOSFET 242 shown in FIG. 11B except that PMOSFET 344 is formed in an N well 350 and NMOSFET 346 is formed in P epi layer 342. PMOSFET 344 and NMOSFET 346 are isolated from P substrate 340 by an isolation structure that includes an N buried layer 356 and N isolation diffusions (NI) 352 and 354. The bias of the isolation structure can be set via an N+ region 358 and is often biased at the most positive supply voltage that power the CMOS devices.
An N-channel lightly-doped lateral DMOSFET 348 includes an N+ region 360 as the source, a P+ region 364, a P-body 362 and a portion of P epi layer 342 as the body, and an N− lightly doped drain region 366, and N well 368 and an N+ region 370 as the drain. A channel is formed in P well 362 and P epi layer 342 under a gate 372. NMOSFET 348 is not isolated from P substrate 340.
A common feature of the devices shown in FIGS. 11A-11E is that they generally require lengthy thermal diffusions in order to make connections through the epi layer. These connections may be required to form isolation regions or to connect to buried layers which function as integral components of the devices. Providing high breakdown voltages generally requires a thicker epi layer and more lengthy thermal processes. The thermal processes all produce lateral as well as vertical dopant spreading, both in the isolation regions that are implanted from above and the buried layers that up-diffuse from below. This lateral dopant spreading limits the spacing and packing density that is achievable with these prior art processes.
Thus, as the feature sizes of the devices themselves decrease, there is a corresponding need for a process that permits the devices to be more densely packed on the surface of the wafer.